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E2E1028-27-Y5
Semiconductor MSM66507/66P507
Semiconductor OLMS-66K Series 16-Bit Microcontroller
This MSM66507/66P507 version: Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM66507/66P507 is a high-performance 16-bit microcontroller that employs OKI original nX-8/500 CPU core. The MSM66507/66P507 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, a pulse-width modulator (PWM), and I/O ports.
FEATURES
* Program memory space Internal ROM * Data memory space Internal RAM * High-speed execution Minimum instruction execution time * Powerful instruction set : : : : 64K bytes 48K bytes 64K bytes 1.5K bytes
* Abundant addressing modes
: 167ns (@24MHz) : Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic operation instructions ROM table reference instructions : Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate value addressing
* I/O port Analog input port : 1 port 10 bits Input-output port : 7 ports 8 bits, 1 port 3 bits (Each bit can be assigned to input or output.) * Flexible timers Free run counters : 19-bit 1, 16-bit 1 19-bit CAP with a divider :4 16-bit double buffer RTO :4 16-bit RTO/PWM :2 16-bit CAP/RTO :2 * 8-bit general timer :1 8-bit event counter :1 * 16-bit PWM :4 Input clock divider :2 * Serial ports UART mode with BRG :1 Synchronous/UART switchable mode with BRG :1 * 10-bit A/D converter : 10 channels 1/24
Semiconductor
MSM66507/66P507
* Transition detector :6 * Watchdog timer :1 * Interrupts Nonmaskable :1 Maskable : Internal 28/external 2 (4-level priority can be set) * ROM window function * Standby modes HALT mode STOP mode * Package 84-pin plastic QFJ (PLCC) (QFJ84-P-S115-1.27-B) (Product name: MSM66507-JS-B) (Product name: MSM66P507-JS-B) indicates the code number.
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BLOCK DIAGRAM
Semiconductor
P2.0/RTO4 P2.5/RTO9 P2.6/FTM10 P3.0/FTM11A P3.1/FTM11B P3.3/FTM11D P3.4/CAP0 P3.7/CAP3 P6.2/RXD1 P6.3/TXD1 P6.4/RXC1 P6.5/TXC1 P6.6/RXD0 P6.7/TXD0 P7.4/PWM0 P7.7/PWM3 AVDD VREF AGND AI0 AI9 P4.0/ETMCK P4.1/ECTCK P4.2/TRNS0 P4.7/TRNS5 P6.0/INT0 P6.1/INT1 NMI P7.3/CLKOUT EVENT TIMER TRANSITION DETECTOR SYSTEM CONTROL INTERRUPT RES OSC1 OSC0
P7 P6 P5 P4 P3 P2 P1 P0
FLEXIBLE TIMER
CONTROL REGISTERS SSP LRB
CPU CORE RAM 1.5K BYTES PSW PC MEMORY CONTROL POINTING R. LOCAL R. ROM 48K BYTES
BUS PORT CONTROL
EA ALE PSEN RD/P7.1 WR/P7.0 WAIT/P7.2 AD0/P0.0 AD7/P0.7 A8/P1.0 A15/P1.7
SERIAL PORT ALU PWM ALU CONTROL A/D CONVERTER ACC, etc. INSTRUCTION DECODER
PORT CONTROL
MSM66507/66P507
OE
PERIPHERAL WDT
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PIN CONFIGURATION (TOP VIEW)
Semiconductor
TRNS4/P4.6 TRNS5/P4.7 P5.0 P5.1 P5.2 NMI RES EA VDD AVDD AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 AI9 AGND 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11
VREF INT0/P6.0 INT1/P6.1 RXD1/P6.2 TXD1/P6.3 RXC1/P6.4 TXC1/P6.5 RXD0/P6.6 TXD0/P6.7 GND OSC0 OSC1 ALE PSEN WR/P7.0 RD/P7.1 WAIT/P7.2 CLKOUT/P7.3 PWM0/P7.4 PWM1/P7.5 PWM2/P7.6
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
P4.5/TRNS3 P4.4/TRNS2 P4.3/TRNS1 P4.2/TRNS0 P4.1/ECTCK P4.0/ETMCK P3.7/CAP3 P3.6/CAP2 P3.5/CAP1 P3.4/CAP0 GND P3.3/FTM11D P3.2/FTM11C P3.1/FTM11B P3.0/FTM11A P2.7 P2.6/FTM10 P2.5/RTO9 P2.4/RTO8 P2.3/RTO7 P2.2/RTO6
84-Pin Plastic QFJ (PLCC)
MSM66507/66P507
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P2.1/RTO5 P2.0/RTO4 OE P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9 P1.0/A8 VDD P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P7.7/PWM3
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Semiconductor
MSM66507/66P507
PIN DESCRIPTION
Symbol P0.0-P0.7/ AD0-AD7 P1.0-P1.7/ A8-A15 P2.0-P2.5/ RTO4-RTO9 P2.6/FTM10 P2.7 P3.0-P3.3/ FTM11A-FTM11D P3.4-P3.7/ CAP0-CAP3 P4.0/ETMCK P4.1/ECTCK P4.2-P4.7/ TRNS0-TRNS5 P5.0-P5.2 P6.0/INT0 P6.1/INT1 P6.2/RXD1 P6.3/TXD1 P6.4/RXC1 P6.5/TXC1 P6.6/RXD0 P6.7/TXD0 P7.0/WR P7.1/RD P7.2/WAIT P7.3/CLKOUT P7.4-P7.7/ PWM0-PWM3 AI0-AI9 AVDD VREF AGND OSC0 OSC1 Type I/O Description P0: 8-bit Input-output port. Each bit can be assigned to input or output. AD: When an external memory is used, these pins output the lower 8 bits of the address. These pins also input or output the data. P1: 8-bit Input-output port. Each bit can be assigned to input or output. A: When an external memory is used, these pins output the upper 8 bits of the address. P2: 8-bit Input-output port. Each bit can be assigned to input or output. RTO: Output pin for real time output FTM10: Capture input pin or real time output pin P3: 8-bit Input-output port. Each bit can be assigned to input or output. FTM11A: Capture input pin or real time output pin FTM11B-D: 4-port real time output pin CAP : Capture input pin P4: 8-bit Input-output port. Each bit can be assigned to input or output. ETMCK: External clock input pin of 8-bit general timer ECTCK: External clock input pin of 8-bit event counter TRNS: Transition detector input pin P5: 3-bit Input-output port. Each bit can be assigned to input or output. P6: 8-bit Input-output port. Each bit can be assigned to input or output. INT0, 1: External interrupt request input pin RXD1 : SCI1 Receiver data input pin TXD1 : SCI1 Transmitter data output pin RXC1 : SCI1 Receiver circuit clock pin TXC1 : SCI1 Transmitter circuit clock pin RXD0 : SCI0 Receiver data input pin TXD0 : SCI0 Transmitter data output pin P7: 8-bit Input-output port. Each bit can be assigned to input or output. WR: Write strobe output pin for external data memory RD: Road strobe output pin for external data memory WAIT: CPU wait request input pin when accessing external data memory CLKOUT: Output pin for supplying a clock to peripheral circuits PWM: PWM output pin Analog signal input only pin for A/D converter Power supply input pin for A/D converter Reference voltage input pin for A/D converter GND input pin for A/D converter Basic clock oscillation pin Basic clock oscillation pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I I I I I O
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Semiconductor
MSM66507/66P507
PIN DESCRIPTION (Continued)
Symbol ALE PSEN Type O O Description Timing pulse output pin to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory Strobe pulse output pin to fetch to external program memory Normally, when P0, P1, and P7.4-P7.7 are in an output state and the OE pin is "H" level, the ports go to a high impedance state. When OE pin is "L" level, the ports output "H" or "L" level. However, when P0, P1, and P7.4-P7.7 are in an input state, these ports are not under the influence of OE pin. Nonmaskable interrupt request input pin RESET input pin Low-active reset input pin Normally set to "H" level. If set to "L" level, the program memory goes to external access mode and accesses external program memory. Power supply pin Ground pin
OE
I
NMI RES EA VDD GND
I I
I I I
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Semiconductor
MSM66507/66P507
REGISTERS
Accumulator
15 ACC 0
Control Register (CR) Program Status Word
15 PSW
0
Program Counter Local Register Base System Stack Pointer
Bit 15 : Carry flag (CY) Bit 14 : Zero flag (ZF) Bit 13 : Half carry flag (HC) Bit 12 : Data descriptor (DD) Bit 11 : Sign flag (S) Bit 10 : Master interrupt priority flag (MIP) Bit 9 : Overflow flag (OV) Bit 8 : Master interrupt enable flag (MIE) Bit 7-3 : User flag Bit 2-0 : System control base 2-0 (SCB2-0) 15 0 PC LRB SSP
15
0
Pointing Register (PR) Index Register 1 Index Register 2 Data pointer User Stack Pointer
X1 X2 DP USP
Local Register
7 ER0 ER1 ER2 ER3 R1 R3 R5 R7 07 R0 R2 R4 R6 0
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Semiconductor
MSM66507/66P507
SFR
Address [H] 0000 0001 0002 0003 0004 0005 0006 0007 0010 0011I 0012I 0014 0015I 0018I 001C 001DI 001EI 0020 0021 0022 0023 0024 0025I 0026 0027 0028 0029 002A 002B 002C 002DI 002E 002F Name System stack pointer Local register base Program status word Accumlator ROM window register RAM ready control register ROM ready control register Stop code acceptor Standby control register Peripheral control register Watchdog timer TBC Clock dividing counter TBC Clock dividing register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 0 mode register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Symbol SSP LRBL LRBH PSWL PSWH ACCL ACCH ROMWIN RAMRDY ROMRDY STPACP SBYCON PRPHF WDT TBCKDVC TBCKDVR P0 P1 P2 P3 P4 P5 P6 P7 P0IO P1IO P2IO P3IO P4IO P5IO P6IO P7IO
8/16-bit R/W Operation Reset FF FF
Undefined 8/16 R/W 00 00 00 00 00 FF FF "0" C8 * Halt F0 F0 00 00 00 00 00 F8 00 00 00 00 00 00 00 F8 00 00
W R/W W R 8
R/W
8/16
Note: A I mark in the address column shows that there is a bit that does not exist in its register. * The initial values of PRPHF (SFR=18H) are as follows : When RES pin is reset : VBFF (bit 6) is set to "1" and CKOUT1 and 0 are set to "0". When reset by the WDT or BRK instruction or by operation code trap : VBFF (bit 6) keeps the value just before reset and CKOUT 1 and 0 are set to "0". In any cases, the state of the OE pin is read for OERD (bit 7).
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Semiconductor
MSM66507/66P507
SFR (Continued)
Address [H] 0031 0032I 0033 0034 0036 0037 0038 0039I 003AI 0040 0041 0042 0044 0045 0046 0048 0049 004A 004EI 004FI 0050 0051 0052 0053 0054 0056 Name Port 1 secondary function control register Port 2 secondary function control register Port 3 secondary function control register Port 4 secondary function control register Port 6 secondary function control register Port 7 secondary function control register TRNS control register 0 TRNS control register 1 Transition detector Interrupt request register 0 Interrupt request register 1 Interrupt enable register 0 Interrupt enable register 1 Interrupt request flag disable register 0 Interrupt request flag disable register 1 NMI control register External interrupt control register Interrupt priority control register 00 Interrupt priority control register 01 Interrupt priority control register 10 Interrupt priority control register 11 Symbol P1SF P2SF P3SF P4SF P6SF P7SF TRNSCON0 TRNSCON1 TRNSIT IRQ0L IRQ0H IRQ1L IE0L IE0H IE1L IRQD0L IRQD0H IRQD1L NMICON EXICON IP00L IP00H IP01L IP01H IP10L IP11L R/W Operation 8 8/16 8 8/16 8 8/16 8 R/W 8/16 8 8/16 8
8/16-bit
Reset 00 80 00 00 00 00 00 F0 C0 00 00 00 00 00 00 00 00 00 FC or 7C F0 00 00 00 00 00 00
8/16
8
Note: A I mark in the address column shows that there is a bit that does not exist in its register.
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Semiconductor
MSM66507/66P507
SFR (Continued)
Address [H] 0060 0061 0062I 0063I 0064I 0065 0066 0068 0069 006AI 006BI 006C 006D 006E 0070I 0071 0072 0073 0080 0081 0082 0083 0084 0085 0086 0087 Name SCI0 timer counter SCI0 timer register SCI0 timer control register SCI0 transmission control register SCI0 reception control register SCI0 transmission and reception buffer register SCI0 status register SCI1 timer counter SCI1 timer register SCI1 timer control register SCI1 transmission control register SCI1 reception control register SCI1 transmission and reception buffer register SCI1 status register 8-bit general timer control register 8-bit event counter 8-bit general timer counter 8-bit general timer register PWR0 buffer register PWR1 buffer register PWR2 buffer register PWR3 buffer register Symbol S0TM S0TMR S0CON ST0CON SR0CON S0BUF S0STAT S1TM S1TMR S1CON ST1CON SR1CON S1BUF S1STAT GTMCON GEVC GTMC GTMR PW0BF PW1BF PW2BF PW3BF 8/16
8/16-bit R/W Operation
Reset 00 00 02 82 12 Undefined 00 00 00 02 80 00 Undefined 00 30 00 00 00 00 00 00 00 00 00 00 00
8/16
8
8/16
R/W
8
Note: A I mark in the address column shows that there is a bit that does not exist in its register.
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Semiconductor
MSM66507/66P507
SFR (Continued)
Address [H] 0098 009A 009B 009C 009D 009EI 009FI 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8I 00B9I 00BAI 00BBI 00BC 00BDI Name PWM interrupt control register PWM control register 0 PWM control register 1 PWM clock counter PWM clock register PWM RUN Register PWM active register Timer register 0 Timer register 1 Timer register 2 Timer register 3 Timer register 4 Timer register 5 Timer register 6 Timer register 7 Timer register 8 Timer register 9 Timer register 10 Timer register 11 TMR0 lower 3-bit TMR1 lower 3-bit TMR2 lower 3-bit TMR3 lower 3-bit TM setting register Symbol PWINTCON PWCON0 PWCON1 PWDVC PWDVR PWRUN PWACT TMR0 TMR1 TMR2 TMR3 TMR4 TMR5 TMR6 TMR7 TMR8 TMR9 TMR10 TMR11 TMR0L TMR1L TMR2L TMR3L TMSELL TMSELH R/W 16 R/W Operation 8 8/16
8/16-bit
Reset 00 00 00 00 00 30 F0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1F 1F 1F 1F 00 F0
8
8/16
Note: A I mark in the address column shows that there is a bit that does not exist in its register.
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Semiconductor
MSM66507/66P507
SFR (Continued)
Address [H] 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9I 00CA 00CB 00CC 00CD 00CE 00CFI 00D0I 00D1I 00D2 00D8I 00D9I 00DAI 00DBI 00DCI 00DDI 00DEI 00DFI 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00ECI 00EDI 00EEI 00EFI Name TMR4 buffer register TMR5 buffer register TMR6 buffer register TMR7 buffer register Timer control register Timer counter 0 lower 3-bit Timer counter 0 Timer counter 1 Capture control register 0 Capture control register 1 Event control register TMR mode register Event dividing counter 0 Event dividing counter 1 Event dividing counter 2 Event dividing counter 3 EVDV0 buffer register EVDV1 buffer register EVDV2 buffer register EVDV3 buffer register A/DC result register 0 A/DC result register 1 A/DC result register 2 A/DC result register 3 A/DC result register 4 A/DC result register 5 A/DC result register 6 A/DC result register 7 A/DC result register 8 A/DC result register 9 A/DC result register lower 0 A/DC result register lower 1 A/DC result register lower 2 A/D interrupt control register A/DC control register L A/DC control register H Symbol TMR4BF TMR5BF TMR6BF TMR7BF TMCON TM0L TM0 TM1 CAPCON0 CAPCON1 EVNTCONL EVNTCONH TMRMODE EVDV0 EVDV1 EVDV2 EVDV3 EVDV0BF EVDV1BF EVDV2BF EVDV3BF ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 ADCR8 ADCR9 LADCR0 LADCR1 LADCR2 ADINTCON ADCONL ADCONH R/W 8/16 8 8/16 R/W
8/16-bit Operation
Reset 00 00 00 00 00 00 00 00 00 1F 00 00 00 00 00 F0 88 88 00 C0 C0 C0 C0 C0 C0 C0 C0
8
8/16
*8/16 R Undefined
8 R/W
F0 80 80
Note: A I mark in the address column shows that there is a bit that does not exist in its register. * 8/16 means a special word manipulation. (For details, refer to the User's Manual.)
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Semiconductor
MSM66507/66P507
SFR (Continued)
Address [H] 00F0I 00F1I 00F2I 00F3I 00F4I 00F5I 00F6I 00F7I 00F8 00FE 00FF Name RTO control register 0 RTO control register 1 RTO control register 2 RTO control register 3 RTO control register 4 RTO control register 5 RTO control register 6 RTO control register 7 RTO control register 8 Emulator using area* Symbol RTOCON0 RTOCON1 RTOCON2 RTOCON3 RTOCON4 RTOCON5 RTOCON6 RTOCON7 RTOCON8 R/W Operation Reset F8 F8 F8 F8 8/16 R/W FC FC F8 F8 8 00
8/16-bit
Note: A I mark in the address column shows that there is a bit that does not exist in its register. * For the emulation using area, if the write is manipulated, the write data becomes invalid, and if the read is manipulated, the read data becomes undefined.
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Semiconductor
MSM66507/66P507
ADDRESSING MODES
The MSM66507/66P507 provides independent 64K-byte data and 64K-byte program spaces with various types of addressing modes. These modes are shown below, for both RAM (for data space) and ROM (for program space). 1. RAM Addressing Mode (for data space) 1.1 Register Addressing
Example INC USP
1.2 Page Addressing a) sfr page
Example LA, sfr IRQ0
b) Fixed page
Example
ST A, fix 0C0H
c) Current page
Example
ROR off 078H
1.3 Direct Data Addressing
Example
CLR dir 780H

USP
SFR 0000H 0040H RAM 0200H 02C0H
RAM
00H
78 H
RAM
0700H 0780H
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Semiconductor
1.4 Pointing Register Indirect Addressing a) DP/X1 indirect
Example
XCHG A, [DP]
DP
b)
Post increment DP indirect
Example
ADD A, [DP+]
DP After access, DP is incremented by 2.
c)
Post decrement DP indirect
Example
SUB A, [DP-]
DP After access, DP is decremented by 2.
d)
DP/USP indirect with 7-bit displacement
Example
AND A, 12[DP]
DP
e)
X1/X2 indirect with 16-bit base
Example
XOR A, 1234H[X1] X1
f)
X1 indirect with 8-bit register (AL, R0) displacement
Example
OR A, [X1+AL]
X1

RAM RAM RAM -64 to +63 RAM 0 to 65535 RAM
MSM66507/66P507
AL
RAM
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Semiconductor
1.5 Special Bit Area Addressing a) Fixed page SBA area (02C0H to 02FFH)
Example
SB sbafix 2D1H.3
b) Current page SBA area (C0H to FFH)
Example
RB sbaoff 2E9H.7
2. ROM Addressing Mode (for program space) 2.1 Immediate Addressing
Example
MOV SSP, #7FFH
2.2 Table Data Addressing a) Direct
Example LC A, 5678H
b) RAM addressing indirect
Example
CMPC A, [USP]
USP
c) RAM addressing indirect with 16-bit base
Example
LC A, 1234H[ER0] RAM ER0

RAM 02C0H 02D1H RAM C0H E9H
ROM
Address
MSM66507/66P507
xxxxH
ROM
5678H
ROM
0 to 65535
ROM
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Semiconductor
MSM66507/66P507
MEMORY MAPS
Program Memory Space
0000H 0000H Vector Table Area (74 bytes) 0049H 004AH Internal ROM Area (48K bytes) 0069H 006AH VCAL Table Area (32 bytes)
0FFFH 1000H BFFFH C000H ACAL Area (2K bytes) 17FFH 1800H External Memory (16K bytes)
FFFFH
BFFFH
Data Memory Space
0000H 00FFH 0100H 01FFH 0200H 02FFH 0300H 07FFH 0800H 09FFH 0A00H 0FFFH 1000H
SFR Area Reserved Area FIX Area Internal RAM Area Area where local register can be set 01FFH 0200H 0208H 0210H 0238H 0240H External Memory Area Area where ROM window can be set 02C0H SBA Area (64 bytes) Area where SB, RB, JBS, and JBR instructions can be accessed efficiently. Reserved Area
X1 X2 DP USP X1 X2 DP USP X1 USP X1 X2 DP USP
SCB=0 SCB=1
Pointing Register Set
SCB=7
FFFFH
0300H
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Semiconductor
MSM66507/66P507
ABSOLUTE MAXIMUM RATINGS
(Ta=25C) Parameter Digital Power Supply Voltage Input Voltage Output Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Power Dissipation Storage Temperature Symbol VDD VI VO AVDD VREF VAI PD TSTG Ta=85C Per package Per output -- GND=AGND=0V Condition Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to AVDD+0.3 -0.3 to VREF 1300 50 -50 to +150 mW C Unit
V
RECOMMENDED OPERATING CONDITIONS
Parameter Digital Power Supply Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency Ambient Temperature Fan Out Symbol VDD AVDD VREF VAI VDDH fOSC Ta N Condition fOSC24MHz VDD=AVDD -- -- fOSC=0Hz Ta=-40 to +85C VDD=5V10% Ta=-20 to +70C fOSC24MHz MOS load TTL load P0 P1 to P7 Range 4.5 to 5.5 4.5 to 5.5 AVDD-0.3 to AVDD AGND to VREF 2.0 to 5.5 0 to 28 0 to 32 -40 to +85 20 2 1 Unit
V
MHz C -- -- --
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Semiconductor
MSM66507/66P507
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD=5V10%, Ta=-40 to +85C) Parameter H Level Input Voltage H Level Input Voltage H Level Input Voltage L Level Input Voltage L Level Input Voltage L Level Input Voltage H Level Output Voltage H Level Output Voltage L Level Output Voltage L Level Output Voltage Input Leakage Current Input Current Input Current H Level Output Current H Level Output Current L Level Output Current L Level Output Current Input Capacitance Output Capacitance Analog Reference Power Supply Voltage Power Consumption (in STOP mode) Power Consumption (in HALT mode) Power Consumption *1 *2, 5, 6 *7 *1 *2, 5, 6 *7 *1, 4 *2 *1, 4 *2 *3, 6 *5 *7 *1, 4 *2 *1, 4 *2 IOH VO=2.4V IOL ILO CI CO IREF IDDS IDDH IDD VO=VDD/0V f=1MHz, Ta=25C A/D in operation A/D stopped VDD=2V, Ta=25C *8 *8 fOSC=24MHz No load IIH/IIL VI=VDD/0V VOH VOL IO=-400uA IO=-200uA IO=3.2mA IO=1.6mA VIL - VIH - Symbol Condition Min. 2.2 0.80VDD 0.85VDD -0.3 -0.3 -0.3 VDD-0.4 VDD-0.4 - - - - - -2 -1 10 5 - - - - - - - - - Typ - - - - - - - - - - - - - - - - - - 5 7 - - 0.2 1 25 55 Max. VDD+0.3 VDD+0.3 VDD+0.3 0.8 0.2VDD 0.15VDD - - 0.4 0.4 1/-1 1/-250 15/-15 - - - - 2 - - 4 10 10 100 60 130 A pF mA A A mA A V Unit
Output Leakage Current *1, 2, 4
mA
*1. Applied to P0 *2. Applied to P1-P7 *3. Applied to Ain *4. Applied to ALE, PSEN *5. Applied to RES *6. Applied to EA, OE, NMI *7. Applied to OSC0 *8. Ports for input pins are VDD or GND, otherwise no load.
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Semiconductor AC Characteristics * External program memory control
MSM66507/66P507
(VDD=5V10%, Ta=-40 to +85C) Parameter Clock Pulse Width (OSC) ALE Pulse Width PSEN Pusle Width PSEN Pulse Delay Time Low Address Setup Time Low Address Hold Time High Address Delay Time High Address Hold Time Instruction Setup Time Instruction Hold Time Symbol toW tAW tPW tPAD tAAS tAAH tAAD tAPH tIS tIH CL=50PF Condition - Min. 20.833 3toW-10 4toW-10 toW-5 2toW-10 toW-5 toW-0 toW-0 35 0 Max. - - - toW+5 2toW+10 toW+5 toW+10 toW+10 - toW-10 ns Unit
* External data memory control
(VDD=5V10%, Ta=-40 to +85C) Parameter Clock Pulse Width (OSC) ALE Pulse Width RD Pusle Width WR Pulse Width RD Pulse Delay Time WR Pulse Delay Time Low Address Setup Time Low Address Hold Time High Address Setup Time High Address Hold Time High Address Hold Time Memory Data Setup Time Memory Data Hold Time Data Setup Time Data Hold Time Symbol toW tAW tRW tWW tRAD tWAD tAAS tAAH tAAD tARH tAWH tMS tMH tDD tDH CL=50PF Condition - Min. 20.833 3toW-10 4toW-10 4toW-10 toW-5 toW-5 2toW-10 toW-5 toW-0 toW-0 toW-0 35 0 toW-0 toW-0 Max. - - - - toW+5 toW+5 2toW+10 toW+5 toW+10 toW+10 toW+10 toW-10 toW+10 toW+10 ns Unit
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Semiconductor
MSM66507/66P507
CLK
toW ALE
PSEN
AD 0-7
A 8-15
RD
AD 0-7
A 8-15
WR
AD 0-7
A 8-15
, ,, , , ,,
toW tAW tPAD tPW PC 0-7 INST 0-7 tIS tIH tAAS tAAH PC 8-15 tAAD tAPH tRAD tRW RAP 0-7 DIN 0-7 tAAS tAAH tMS tMH RAP 8-15 tAAD tARH tWAD tWW RAP 0-7 DOUT 0-7 tAAS tAAH tDH RAP 8-15 tAAD tDD tAWH
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Semiconductor
MSM66507/66P507
A/D Converter Characteristics
(AVDD=VDD=VREF=5V10%, AGND=GND=0V, Ta=-40 to +85C) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to the recommended circuit (Figure1). Analog input source impedance RI < 5kW = tCONV=512f/CH Refer to the measuring circuit (Figure 2). by ADTM set data f=1/fOSC Min. - - - 0 - - 256f Typ. - - - - - - - Max. 10 3 1 +3 -3 1 768f s/CH LSB Unit Bit
Reference Voltage +
- + Analog input 0.1F
0.1 F VREF AVDD
47W VDD +
0.1 F 47 F
+5V
RI
0.1 F
47 F
AI 0-9
AGND
GND
0V
RI (Analog input source impedance) < 5kW =
Figure 1 Recommended Circuit
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Semiconductor
MSM66507/66P507
- + Analog input
5kW AI0 AI1
0.1F
Crosstalk is defined as the difference between the A/D conversion result when impressing the identical analog input to AI0-AI9 and the A/D conversion result in the circuit in the left figure.
AI9
VREF or AGND
Figure 2 Crosstalk Measuring Circuit
Definitions of Terms 1. Resolution The minimum distinguishable analog input value. For 10 bits, 210=1024, i.e. (VREF-AGND) / 1024 2. Linearity Error The variance between the ideal conversion characteristics as a 10-bit A/D converter and the actual conversion characteristics. (Quantized error is therefore not included.) 3. Differential Linearity Error The smoothness of the conversion. The width of analog input voltage corresponding to the change by one bit of digital output is 1 LSB=(VREF-AGND) / 1024 ideally. The variance between this ideal bit size and bit size at arbitrary point in the conversion range. 4. Zero Scale Error The variance between the ideal conversion characteristics at the switching point of digital output "000H to 001H" and actual conversion characteristics. 5. Full Scale Error The variance between the ideal conversion characteristics at the switching point of digital output "3FEH to 3FFH" and actual conversion characteristics.
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Semiconductor
MSM66507/66P507
PACKAGE DIMENSIONS
(Unit : mm)
QFJ84-P-S115-1.27-B
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 6.30 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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